1. Field of the Invention
The invention relates to data-processing systems, and more particularly, to a high-performance, parallel-processing system.
2. Description of the Prior Art
In the past, data-processing systems utilizing parallel processing have met with limited commercial success. Consider, for example, the Illiac IV, designed by Burroughs Corporation. The Illiac IV utilizes an array of 64 processors, each with a local memory, operating in parallel with each processor executing the same instruction. This is known as a single-instruction-stream multiple data stream (SIMD) system. The Illiac IV is a very powerful computer and has been used to solve difficult scientific problems such as those involving fluid flow. The Illiac IV system is difficult to program because of the SIMD architecture. A more important disadvantage, however, is that the system lacks reliability. The mean time to failure is measured in hours.
Other parallel systems have been built for specific applications and would not be useful in more general, scientific applications. The high-performance data-processing systems that have been successful fall within one of two categories. The first category are those that are very high-speed uniprocessors that are heavily pipelined. The second category are special-purpose, inexpensive array processors that off-load data from a general processor for scientific processing. The Cray 1 and Cyber 205 fall within the first category, and the Floating-Point Systems' AP-120 falls within the second category.
These prior systems have several disadvantages. For example, the Cray 1 system approaches the limits imposed by physical constants. Wires must be kept short and the processor must be tuned to get full performance. Programs must be vectorized to take advantage of the pipeline structure. If this is not done, the Cray 1 will run much slower than its maximum speed. Finally, because of its size and sensitivity, the Cray 1 requires expensive, special handling such as reinforced floors, liquid cooling, and hand tuning.
The second category of prior systems (array-processors) is also subject to the physical limits imposed by the speed of the single or small number of processors that make up the array.
Current attempts to utilize the multiple-instruction stream, multiple-data-stream (MIMD) approach to parallel processing runs into two significant problems. The first is that by using standard ECL circuits, the size of the system is limited by reliability constraints, and therefore such a system would not be operable with tens or hundreds of processors. The second problem is that current systems use a single memory shared by all the processors. This has the advantage of allowing a programmer to keep all of the data in one memory, but has a major disadvantage of limiting the system performance to the bandwidth of a single computer system.
It is a primary object of the present invention to provide a new data-processing architecture and apparatus utilizing parallel processing, with a system performance that is above the level of modern supercomputers, but is within the price range of a small mainframe computer.